Universal memory device having a profile storage unit

ABSTRACT

A universal memory device is presented that provides adaptability to existing hardware and software environments. The memory can “mimic” existing memory technology combining the advantages of integrating all memory capacity into one single technology and still providing the implicit protections and access characteristics known from the different existing memory technologies. The memory device comprises a memory having low-latency, rewritable, non-volatile memory cells, a profile storage unit connected with the memory and comprising access information allocated to a set of request information elements (request profile), such that the access information indicates whether an access request to said memory, the access request having the request profile, is to be allowed or rejected, and an access control unit communicating with the profile storage unit and the memory, and adapted to allow or reject an incoming access request in dependence on the access information allocated to the request profile of the access request.

The invention relates to a memory device with low-latency, non-volatile,rewritable memory cells, and, in particular, to a universal memorydevice.

Current digital systems typically employ a multitude of differentmemories. For processing, caching and buffering, Static Random AccessMemory (SRAM) and Dynamic Random Access Memory (DRAM) are used. Forexecutable code, on the other hand, Read-Only Memory (ROM), Erasable andElectronically Erasable Programmable ROM (EPROM, EEPROM), and NOR-Flashare employed. Finally, for persistent data storage, one uses NOR-Flash,NAND-Flash and magnetic or optical disc drives.

The choice of the type of memory is dictated by criteria likeperformance, cost, persistence of stored information after power down,or the ability to rewrite the memory. Often one or more of the mentionedtechnologies are combined into a single package or even in a single chipin an attempt to overcome disadvantages of a particular technology, orto simplify overall system design.

New memory technologies have been developed in an attempt to combineattractive properties of several of the above-mentioned types of memoryin one technology. For instance, Magnetic Random Access Memory (MRAM),Ferroelectric RAM (FERAM), Ovonics Unified Memory (OUM), and to someextent also battery-backed SRAM as well as battery-backed slow-refreshSDRAM share the advantage of combining a rewritable and non-volatilememory space with a low latency. This advance in technology triggeredattempts to also merge in a single memory device different memory useslike caching, persistent data storage, and other types of the usesmentioned in the beginning, that have been performed by different memorydevices to date. The concept of merging different memory uses in asingle memory device with low-latency, non-volatile, rewritable memorycells is also referred to as universal memory. Universal memory isanticipated to lead to a simpler computer design, lower powerconsumption, and lower inventory cost.

However, current hardware (HW) and software (SW) architecturesimplicitly rely on the properties of the different, still prevailingmemory technologies for proper functioning. This will be explained inthe following by way of several examples.

As a first example, the current software design of operating systems forcomputers builds on a property of current typical processing memory,namely, its volatility. Due to the volatility of the processing memory,operating systems of computers provide a re-initialization of theprocessing memory at power-up. As a consequence of this, sincere-initialization is performed anyway, there are no provisions necessaryagainst spurious write operations to the memory during power-down andpower-up of the computer. These spurious writes destroy processing codethat has been loaded previously to the memory and is necessary fornormal operation.

In contrast to processing memory, persistent memory for storage of dataand code, as a second example, typically has explicit or implicitprotections against spurious overwrites during power transitions.Explicit and implicit protections of a memory against write operationsare inherent in a respective memory technology. E.g., the protection ofa ROM device against an overwriting of stored data and code is due tothe physical nature of the storage medium and the technique used forwrite and read operations. Hence, crucial start-up code of a computersystem is stored in a ROM to protect it against getting corrupted duringoperation. Furthermore, dedicated hardware protections may be provided,for instance, by providing a memory device with an electrical contactenabling a write operation and making this contact accessible only inthe manufacturing process for programming the memory device. Inaddition, or alternatively, data stored in persistent memory is oftenhidden in a relatively complicated and/or slow write protocol. A writeoperation to a memory is only enabled if the write protocol is used,thus preventing unintended write operations.

Another example for a typical feature of memory devices, that currentsoftware and hardware design relies on, is that some memory devicesallow Direct Memory Access (DMA) for peripheral hardware. DMA providesan access to the memory independent from the control of a MemoryManagement Unit (MMU) in the central processing unit (CPU) of acomputer. The DMA hardware is a specialized processor, e.g., in acontroller of an I/O device. It transfers data between the memory andthe I/O device without using processing and register capacity of theCPU.

In addition to the implications of existing memory technologiesmentioned, different types of memories may be addressed in differentways. For example, memory related to processing and execution typicallyuses a low-latency, random addressable memory-mapped addressing schemeon the processor. Data storage, however, typically uses I/O addressingin data blocks. This implies a higher latency, but gives a large datacapacity while requiring a relatively small processor address range. I/Oaddressing also has good data streaming properties.

These examples of the implications of the memory technology prevailingto date show that a transition to the sole use of the so calleduniversal memory instead of the various types of memory used todayrequires an adaptation of the hardware design of computers as well as ofthe software design. Thus, while almost ready to enter the market, anddespite of a high potential to merge the plurality of present memorytechnologies into the use of one single technology, universal memory ishard to implement into present hardware and software systems.

It is therefore an object of the present invention to provide auniversal memory device that fits into the present hardware and softwareenvironment.

According to the invention a memory device is provided comprising

a) a memory having a plurality of low-latency, rewritable, non-volatilememory cells forming at least one memory section,

b) a profile storage unit connected with said memory and comprisingaccess information allocated to at least one set of request informationelements (hereinafter request profile), such that said accessinformation indicates whether a request for access to said memory(hereinafter access request), said access request having said requestprofile, is to be allowed or rejected,c) an access control unit communicating with said profile storage unitand said memory, and adapted to allow or reject an incoming accessrequest in dependence on the access information allocated to the requestprofile of the access request.

The basic idea of the present invention is that many applications useimplicit properties of a certain type of conventional memory. Forexample an implicit property of volatile RAM is that all data is lost ifthe device is switched off. This property is used implicitly as asecurity measure. The memory device of the invention builds on the newuniversal memory technology, providing low-latency, rewritable,non-volatile memory capacity, and is adapted or has the ability to adaptto hardware and software environments designed for conventional memorytechnologies.

The memory device of the invention provides adaptability to differenthardware and software architectures by differentiating between aplurality of request profiles. Before showing how adaptability can beachieved this way, the term request profile as used herein is explained.

A request profile comprises a set of request information elements.Request information is, generally speaking, all information related toan access request, indicating for instance the source of the request,i.e., a memory client, the memory section the request is directed to(address information), the type of memory access requested (read and/orwrite), and other information related to the request. Such otherinformation is for instance the time of the request, or a security classinformation transmitted with the request, indicating an authorization toaccess a certain memory section. Request information on a particularaspect of an access request is called a request information element. Arequest information element may comprise one or more bits ofinformation. Further examples of request information elements will begiven below and in the context of the description of preferredembodiments of the invention.

It is important to note that request information is on one handinformation comprised by the request, such as the memory section accessis requested to. However, request information is not limited toinformation of this kind. Request information is on the other hand alsoinformation that is related to the request, but not comprised in thereceived request data, be it command-related data or user data of therequest. Request information of the latter kind, if comprised by arequest profile, is ascertained in an indirect way from the accessrequest. Examples for request information of this latter type are thetime of the request, and the information whether an access requestdirected to the same memory section has been received by the memorydevice before within a defined time span.

A request profile, therefore, can take the form of a data structure,such as a list comprising one or more entries representing requestinformation. A set of request profiles can be represented by a table, inwhich each request profile takes, e.g., one line. Each column of thetable represents one request information element, such as informationelements “write request”, yes or no, “read request”, yes or no, “memoryclient identification”, given by an identification code. In general, anentry in a line of the table, i.e., an information element of a requestprofile, can take the form of a code indicating “yes”, “no”, or specificdata such as a memory client identification number, a password, etc.Obviously, different request profiles can differ in the number ofspecified request information elements. If the set of request profilesserved by the memory device of the invention is structured as a matrix,a code indicating “not specified” may be used for certain informationelements, for instance if providing a password with a request is notnecessary in a specific request profile.

There is no need to stick to a software structure of request profiles. Arequest profile can also be implemented by hardware. For instance,consider request information elements indicating the memory address anaccess request is directed to. A memory address is typicallycommunicated in the form of address bits. Each possible combination ofaddress bits can represent an individual request profile. Suchcombination of address bits can be allocated to access information by acircuit providing a programmable switching element (access flag) foreach possible combination of address bits. The access flag allows orrejects an access request to the memory section corresponding to thecombination of address bits that is contained in the request. This way,in principle, access to each individual memory cell can be controlled.Of course, groups of addresses allocated to the same access flag can bedefined this way, too. In a similar way as address information, everyother combination of request information elements can be allocated to arespective access flag.

It is noted that the functionality of the memory device of the inventiondoes not rely on a specific data structure of a request profile. Forexample, the request profile can comprise an access information elementin addition to request information elements, indicating whether arequest comprising the request information elements of the particularrequest profile is to be admitted or rejected.

A further important element of the memory device of the invention is theaccess control unit. The access control unit ascertains an appropriaterequest profile to an incoming request using the request information ofthat request. Based on the request profile ascertained, the accesscontrol unit allows or rejects the requested memory access.

The memory device of the invention has a memory with low-latency,rewritable, non-volatile memory cells. Thus, as known per se foruniversal memory devices, it combines the advantages of different oldermemory technologies with a high degree of flexibility in the use of thememory. The memory may be based on any of the previously mentioneduniversal-memory technologies, which per se all are well known in theart, or a combination thereof. The invention is not restricted to theuse of these memory technologies, as further technologies providinglow-latency, rewritable, and non-volatile memory may emerge in thefield. The term “low latency” serves to characterize the types ofmemories mentioned in the beginning, differentiating the memory deviceof the present invention also from magnetic hard-disk storage technologywith a high latency in the ms range. Generally, the lower the latency,the more flexibility of use the memory device of the invention offers.For if necessary, the access control unit, as described in the contextof a preferred embodiment, can always provide a higher latency.

As all memory devices, the memory device of the invention is adapted toreceive access requests from at least one external memory client. Anaccess request is any request for access to the memory device, be it toworking data, user information or code stored in the memory, accessprofile information or program code used by the memory device, or toother information stored in the memory device. Among the access requestsare, beside read requests and write requests, further types of accessrequests such as, for instance, a “Clear” command. A “Clear” command isa request to deallocate a memory section such that it is allowed to beoverwritten.

Most access requests specify a memory section they ask access to. Theterm “memory section” comprises, by way of example, a specific memorycell, a memory row, a memory column, a memory block, or any group ofmemory cells, rows or columns or blocks, up to the whole memory. Thus,an access request may be directed to any cell or group of cells in thememory of the memory device of the invention.

In summary, the universal memory of the invention is adapted to beprogrammed to have a plurality of different access characteristics inaccordance with a specific hardware and software environment. The accesscharacteristics to the memory device of the invention can be madedifferent for different memory clients and/or for different memorysections by defining corresponding request profiles. Based on requestprofiles different requests are identified and served or rejected inaccordance with the respective access characteristics. The universalmemory of the invention is therefore adapted to be used in existinghardware and software environments that build on a multitude of memorytypes.

The memory device of the invention can be implemented in differentembodiments.

Preferably, in the memory device of the invention, the requestinformation comprises information indicating a type of request, anexternal memory client from which the request originates, a memorysection the request is directed to, an access authorization, a password,a request protocol type, a time of request, an interface receiving therequest, the length of the request, a time span lapsed since the lastrequest, a security class, or a priority class.

Information about the length of the request is available in manystandard request protocols. It can be used, alone or in conjunction withtime information, to create a form of an access bandwidth restriction.With the aid of security class information that is either contained in arequest or can be deduced from other request information such as thememory client originating the request, write and/or read access can berestricted to certain memory sections while allowed to others. With theaid of priority class information a feature can be realized in whichfrom a number of pending requests the request with the highest priorityclass is served first. This way, the performance of applications can beenhanced.

When different memory uses known from earlier memory technologies arecombined in a single device, it becomes crucial to provide thecorresponding different memory properties and protections inherent inthese technologies. A preferred embodiment of the memory device of theinvention comprises a plurality of interfaces for communication of thememory device with different external memory clients or forcommunication according to different memory uses, each interface beingconnected with the access control unit and allocated to a subset ofrequest profiles.

The interfaces are functional units each providing specific accesscharacteristics by allocating access information to a subset of the setof request profiles reflecting a specific memory use and/orcommunication rules shared with a specific external memory client. Theinterfaces can be provided in the form of hardware or software. Also,some software-differentiated interfaces and some hardware-differentiatedinterfaces may be present. In order to keep the advantages of a lowerbill of materials, more flexibility and lower inventory cost, it isadvantageous to be able to combine different memory uses in a singlememory structure in a programmable rather than a hardwired way. Hardwareprogrammability provides the required flexibility while being a morerobust solution than purely software based solutions. Beside the term“interface”, the term “port” will be used herein with the same meaning.

The ports can be hardware and/or software differentiated. A portpreferably corresponds to a particular memory usage and mimics aconventional memory technology. This combines the advantages of variousprotections and properties of conventional memory technologies asmentioned above with the advantages of being compatible with legacysolutions. The address ranges of the various ports may or may notoverlap.

As a first example of the present embodiment, a specific interface “A”is allocated to read and write requests originating from one specificmemory client “B” that has access rights to only a defined section “C”of the memory. Any read or write request from memory client B isallocated to interface A which will provide the requested access tomemory section C.

As a second example, a specific port “D” is allocated to requestsdirected to a specific memory section “E”. The memory device mimics aRead-Only memory in Section E. Thus, requests directed from any externalmemory client to memory section E are allocated to port D, which willprovide a read access only. If the request is a write request, therequest is rejected at port D by the access control unit.

The ports of the present embodiment are preferably adapted to providememory access characteristics needed in a given hardware and softwarearchitecture, for instance that of a Read-Only Memory, of a DRAM memory,or of a Password-Protected Memory.

By way of defining adequate request profiles and allocated accessinformation the following access characteristics can be provided:

a) Write once, afterwards read access only. This makes it possible tostore protected and/or tamper-free code and data. It provides theequivalent of ROM, PROM, OTP, WORM and EPROM that can typically not berewritten inside the embedded system. This could be implemented as awrite lock flag (or a flag that freezes the current protection settings)that can only be set, but not cleared. But also as a write protect flagthat can only be cleared under special circumstances.

Any irreversible lock mechanism in the access can be provided by specialmeasures during manufacturing and testing, to prevent that the devicemight effectively become unusable when the lock is accidentallytriggered in normal operation. This can be solved by initialization ofthe device through a special pad, or another special condition like astrong external magnetic field in the case of an MRAM memory.

b) “Difficult to write, easy to read”. Flash and EEPROM can often berewritten inside an embedded system through very special measures, buttheir “write-protect” behavior is sometimes still implicitly used by thesystem. This could be implemented as a programmable write protect flag.An actual write operation would have to include removing the write-flag,the write operation itself, and setting the write protect flag again. Anaccidental write would be blocked by the write protect flag.c) Power-on reset clears the content of a certain memory segment duringpower-on. DRAM and SRAM loose their content on power-down. This issometimes used implicitly as a security/privacy feature: no traces leftafter powering down. Note that an explicit user-initiated memory clearbefore power-down may also be possible, but that is not the same. Alsonote that an automatic memory clear of indicated memory segments duringpower-down may seem to be safer than a clear at power-on reset, but maybe difficult to implement reliably in an uncontrolled power failure.d) A read-once property may be a useful feature for some pay-per-viewand for-your-eyes-only schemes. In a standard random access memory thisproperty may be too hard to implement in a useful way, but forblock-access or a paged device it is easily done.e) Write-only memory in a certain segment. Making an “easy to write, butdifficult to read” segment may help in certain tracking orsecurity/privacy schemes like password-storage.f) No-access to a certain segment can be useful, e.g., to expose onlyone certification code to the rest of the system, and only resort to thenext stored alternative when the previous one expires or is revoked.Another application is when the access restriction depends on the port.In that case it can be useful to define a certain segment as forbiddenterritory for one port, and fully accessible for another, or to define amessage passing window with write-only access for one port and read-onlyaccess for another port.g) Password protected access restrictions to (parts of) the memory maye.g. be useful in Digital Right Management, but also in support of theabove modes. These characteristics can e.g. be described by a number offlags or codes.

The memory device of the invention differs from known processor basedMemory Management Units (MMU) in that access restrictions governed by aMMU are independent of the memory itself. The memory moduleadministrated by an MMU can be sold separately, or removed from thesystem and used in a different system. In addition a MMU cannot forceaccess restrictions for other DMA hardware in the system, and cannothandle all of the mentioned access characteristics.

In a further embodiment the access control unit of the memory device ofthe present invention takes the form of a distributed access controlfunction that is implemented in the interfaces. In this embodiment,there is no need for a central access control unit in the memory device.The functionality of the access control unit is distributed over theinterfaces. Each interface is responsible for allocating an incomingrequest to one request profile of the subset of request profiles servedby the particular interface, and for allowing or rejecting the accessrequest in dependence on the allocated request profile.

Preferably, one of the interfaces of the memory device of the presentembodiment is an SRAM-type interface, i.e., a so-called memory-mappedinterface. It is adapted to serve separate connections for address datainput and user data exchange, respectively, between the memory deviceand at least one external memory client. In this embodiment, thememory-mapped interface receives an access request through two separateinput connections. Through a first connection it receives memory addressinformation comprised by the request. Through a second connection itreceives or sends user data. The connections are preferably establishedthrough different pins of the memory device, a pin for each bit in theaddress, and a pin for each bit in the data word. A memory-mappedinterface has the advantage that it provides random access to memorydata with very low latency. As to request profiles for a memory-mappedinterface, access requests directed to the memory-mapped interface maybe differentiated by request information elements indicating enablingsignal levels at one or more address pins of the memory device.

In another embodiment, the memory device comprises an I/O-mappedinterface. In this embodiment, the I/O mapped interface receives addressinformation and user data through only one connection. The interface isadapted to serve a shared connection for address data input and userdata exchange between the memory device and at least one external memoryclient. To separate address information from user data, a separatecontrol connection may be used, for instance through a separate pin inthe form of an AddressEnable pin. To signal that subsequent datareceived at the interface is address data, the signal level at theAddressEnable pin is set to a “high” level. This information may also beused as distinguishing request information for request profilesallocated to the I/O-mapped interface. An I/O-mapped interface has theadvantage to save pins. On the other hand, random access to the memoryis slower than for the memory-mapped interface type. The I/O-mappedinterface may be used for instance to let the memory device of theinvention provide the functionality of a NAND flash memory.

It is within the scope of the invention to provide compatibility to anyknown technology used for memory addressing, among which memory mappedaddressing and I/O addressing are the most prominent and widely usedmethods.

In a further embodiment both a memory-mapped interface and an I/O-mappedinterface are provided. Both interfaces may provide access to the samememory address range, to completely separate memory address ranges, orto overlapping memory address ranges. This is, by the way, a generaladvantage of the memory device of the invention that is not restrictedto the example of memory-mapped and I/O-mapped interfaces. The pins ofthe memory device that serve for exchange of user data with externalmemory clients are preferably shared by the I/O-mapped and thememory-mapped interfaces.

Memory-mapped and I/O-mapped interfaces are two widely used examples ofinterfaces that the memory device of the invention is able to providewith the aid of request profiles. The memory device of the invention cansimilarly provide any other interface types known in the art, alone orin parallel.

The access characteristics of the memory device are in a furtherembodiment of the invention programmable for each port. In anotherembodiment the access characteristics are programmable for each memoryblock, e.g. of 4 KBytes size.

In a further embodiment of the memory device a translation unit isprovided. The translation unit is adapted to translate between one ormore different ways of memory addressing, such as memory mapped vs. I/Omapped. The translation unit allows providing access to the same or twooverlapping memory sections for memory clients using different memoryaddressing types. Only one interface serving one type of memoryaddressing is necessary when the translation unit is present. Thecompatibility may be provided by a programmable address translatorincluded in the interface unit.

The translation unit in an alternative embodiment preferably integratedupstream of the interface unit. It may also be implemented as anexternal unit. This way, the number of pins of the memory device can bereduced.

Flexibility can be provided by programmable access characteristics foreach port (e.g. write protection), and a programmable address range inthe memory structure. The programmability of the access characteristicscan be achieved through a separate bus command, or a special memorysection.

In a further preferred embodiment of the invention a supervisorinterface is provided which is adapted to create or change at least onerequest profile and/or access information allocated thereto, given apredetermined condition. Manipulation of access characteristics isperformed by changing the request profiles concerned and/or accessinformation allocated to these request profiles. Creation of a newrequest profile is preferably accomplished by creating a new line entryin the request profile matrix described earlier, specifying requestinformation elements that distinguish the new request profile from theones already existing. The change of an existing request profile isaccomplished by adding or deleting a request information element, or bychanging the specific value or code of that request information elementin the selected request profile. For example, it is useful when thememory device can trade-off execution code space versus user datastorage space. To accomplish this, the respective address ranges forstorage of execution code and user data defined in the concerned requestprofiles are changed so that, for example, a request to write user datato the memory will also be allowed if directed to a memory section thatwas before used for execution code.

Access restrictions to the access changes could simply be the result ofthe programmable access scheme, where the system simply restrictsfurther access to access programming to only one of the ports. Externalaccess is preferably restricted to only the supervisor interface. Thesupervisor interface can provide defined change authorization toexternal memory clients by appropriate request profiles. In thisembodiment the supervisor interface is adapted to admit or rejectexternal requests for change of a request profile or access information,depending on the request information of the access request from anexternal client. In addition or as an alternative, a password protectionscheme for changes to the access properties can be considered.

Access information is typically a one-bit information element indicatingadmission or rejection. A change of the access information allocated toa request profile simply implies switching the respective informationelement. An example for the use of the change of access information isthe change of code in the memory that is write-protected initially.Write protection is lifted for the programming access to the code andthen reinstated.

However, the authorization to change the request profile or an accessinformation allocated to a request profile must be limited, since suchchange touches core functionalities of the memory device and theconnected hardware relying on the data in the memory. In a furtherembodiment, therefore, the supervisor interface is adapted to admit orreject external requests for change of a request profile, depending onaccess information allocated to at least one predetermined changerequest profile. Special request profiles may be implemented serving todefine the memory clients and/or circumstances that may cause a change acertain group of request profiles or access information. For example,such programming access can be password protected. Programming accesscan be restricted to certain request information elements, to certaintime spans, or to certain events. As an example for an event-triggeredchange, a change of access information may be caused by the event ofhaving served a first write access request to a memory section definedin the corresponding request profile.

In a further preferred embodiment of the invention, said profile storageunit takes the form of a set of access flags, each access flag allocatedto a respective interface, and wherein said access information is givenby one of two possible states of an access flag.

In a further embodiment of the memory device of the invention, accessinformation takes the form of one of two possible states of an accessflag. In this embodiment, the profile storage unit preferably comprisesa set of access flags, each access flag allocated to a respectiverequest profile.

The profile storage unit is in a further embodiment integrated into saidaccess control unit. In an alternative embodiment, it is an integralpart of the memory. In a further embodiment the access control unit isadapted to maintain a current copy of said access storage unit in apredetermined section of the memory.

In a further embodiment the memory device of the invention is adapted toprovide programmable access characteristics per programmable windows.That means, not only the access flags may be programmed through theaddress and data interface, but also the address range of the memorycell array that specific access characteristics are valid for.

The access characteristics can be programmed as an access type permemory block (e.g. of 4 KBytes), and/or per port. E.g., each memoryblock of say 4 KByte could have programmable access flags. Or eachmemory block could have programmable access flags separately for eachport. Or, as mentioned above, each port could have programmable accessflags and a programmable window.

In many cases it is important that the access configuration is stored innon-volatile memory. This can be important for proper system operation,but also for a business model where a single “universal memory devices”can be permanently programmed by the manufacturer or supplier as drop-inreplacement for different existing combo-devices with hardwiredpartitioning between different memory types. (Somewhat comparable to thepractice of “down-stroking” in Hard Disk Drive business.)

In the following, the invention will be described in further detailbased on preferred embodiments with reference to the figures, wherein

FIG. 1 is a simplified block diagram of a first embodiment of a memorydevice according to the invention.

FIG. 2 is a simplified block diagram of a second embodiment of a memorydevice according to the invention.

FIG. 3 is a simplified block diagram of a third embodiment of a memorydevice according to the invention.

FIG. 1 shows in a simplified block diagram as a first preferredembodiment a memory device 10 according to the invention. The memorydevice has a memory cell array 12 of magnetic RAM cells. The memory cellarray 12 is connected to a word-select unit 14 and a section-select unit16. Word-select unit 14 and section-select unit 16 are connected to anaddress and data interface. Address and data interface 18 is furtherconnected to a profile storage unit 20 and an access control unit 22.Address and data interface 18 is an interface of memory device 10 toexternal memory clients.

Word-select unit 14 and section-select 16 operate to select the part ofthe memory that is accessed by an access request. In the presentembodiment, Word-select unit 14 provides a column selection mechanismthat mostly operates in the data path. Section select unit performs arow selection mechanism that only controls the memory array, i.e., isnot in the data path. Both units 14 and 16 use the address informationreceived from address and data interface 18 to select the respectiveword and row as indicated by the address information.

The output signals provided by section select unit 16 for selection of amemory section are fed in parallel to memory cell array 12 and toprofile storage unit 20. Profile storage unit 20 comprises a set ofaccess flags, one access flag for each possible row address. Therefore,each access flags governs the access to one row of the memory cell, andcan be addressed using the same signaling as for the correspondingmemory row of memory cell array 12. Profile storage unit 20 provides asan output signal the state of the selected access flag to access controlunit 22.

For performance reasons, it is advantageous that the access flags areimplemented as fast read-out state registers in the memory addressing.It is also advantageous to have the access flag states in a section ofthe non-volatile memory 12 and to copy the contents of the non-volatileregisters into the fast registers.

The state of each individual access flag can be programmed throughaddress and data interface 18. This way, different memory accesscharacteristics can be given to different parts of the memory. Forinstance a ROM memory and a RAM memory can be implemented in the memorydevice 10 by defining on one hand the address range of the memory cellarray 12 to which random access shall be granted, and on the other handthe address range of memory cell array 12 to which only read accessshall be granted. It is easily seen that other parts of the memory maybe in a similar way be provided with other access characteristics, asdescribed above.

Access control unit 22 operates in the data path to admit or reject theflow of data to or from the memory, depending on the flag state signalit currently receives from profile storage unit 20.

This simple example shows how flexible the memory device can be adaptedto a specific hardware or software environment. Obviously, there is norestriction in the selection mechanism to the matrix-like selectionscheme described above. Any known cell selection technique can be usedwith this embodiment. It is only important that the incoming address isused to select a defined area of the memory and corresponding accessflags. The selected access flag(s) control(s) whether the access isallowed or not. The access flags can be programmed through the addressand data interface

In an alternative embodiment that is not shown the block of access flagsis part of the memory cell array 12. In a further alternative embodimentthe access flag is selected through a special address input line.

FIG. 2 shows in a simplified block diagram as a second preferredembodiment a memory device 30 according to the invention. The memorydevice has a memory cell array 32 of magnetic RAM cells. The memory cellarray 32 is connected to a word-select unit 34 and a combined accesscontrol and profile storage unit 36. Profile storage unit is connectedto a section-select unit 38. Word-select unit 34 and section-select unit38 are connected to an address and data interface 40. Address and datainterface 40 is an interface of memory device 30 to external memoryclients.

The embodiment of FIG. 2 differs from that of FIG. 1 in that accesscontrol and profile storage are integrated into one single unit 36. Inthis embodiment, the access flags operate directly on the section selectof the memory cell array, denying access where needed.

The common feature of the embodiments of FIGS. 1 and 2 is an SRAM-typememory mapped interface. When a write protect flag is active for aparticular section addressed by an access request to the memory, memorywrites to that particular section will be ignored.

An extension of the word select mechanism to include the access flagswould be easy to implement in the embodiments of FIGS. 1 and 2. Thiscould correspond to a situation where the access flags are programmed asan extension of the corresponding section; the address lines forselecting the section are the same as those for selecting thecorresponding access flag.

The embodiments of FIGS. 1 and 2 suggest that the section governed by anaccess flag is equal to a row-addressing unit in the memory array.Obviously, that is not necessarily the case. E.g., the access section ofmemory cell array 12 or 32, respectively, could be standardized to aparticular size, while the row and column organization of the memoryarrays is optimized for a certain performance or memory capacity.

The memory devices shown in FIGS. 1 and 2 can be extended to provideboth an SRAM-type memory mapped interface and an I/O mapped interface.This extension is shown in FIG. 3 for a memory device 50, that otherwiseresembles the embodiment of FIG. 2.

The following description concentrates on the differences to theembodiments of FIGS. 1 and 2. The memory device 50 has both an SRAM-typeinterface 52 and an I/O mapped interface 54. Both interfaces give accessto the same memory cell array 56. An addressing register 58 of the I/Omapped interface 54 contains address bits. In addition, it also containsa special bit for selecting the profile storage unit 60, implemented inthis embodiment in the form of a set of access protection registers andone or more bits to indicate different access IDs. For instance, twobits that can be used to indicate four different access IDs. Of course,any other number of bits can be used to indicate a lower or highernumber of access IDs. Each access ID is allocated to one external memoryclient. The relation between an ID and a client can be enforced throughcomputer hardware or software.

Each Byte of the access protection registers in profile storage unit 60governs the access of a 4 KByte section of the memory 56. There are asmany Bytes in the access protection registers of profile storage unit 60as there are sections in the memory. In one access protection registerbyte there are 4 write protect flags and 4 read protect flags. Each flaggoverns the access for the corresponding access ID. Access through theSRAM interface 52 is controlled by the same bits as access through theI/O interface 54, for instance with access ID 00.

A write request that violates a write access flag is ignored, and a readrequest that violates a read access flag results in a fixed answer(e.g., all binary zeroes). Every access violation triggers an interruptpin on the interface.

The memory device of the invention has been described by way of severalembodiments. Even though the described embodiments focus on computerapplications, the use of the present invention is not restricted tocomputers. Any digital system is within the scope of application of thememory device of the invention.

The memory device of the invention take the form of a memory componentembedded in an integrated circuit, a separately packaged memorycomponent on a systems board, or a separately packaged, removableperipheral memory product.

1. A memory device comprising: an interface for receiving access requests, the interface having an address output to an address path and a data output to a data path, wherein address information is carried on the address path and data for writing to memory or data read from memory is carried on the data path; a memory cell array having a plurality of low-latency, rewritable, non-volatile memory cells forming at least one memory section; a word-select unit connected in the data path and to the address path and between the interface and the memory cell array to provide column selection; a section-select unit connected to the address path and between the interface and the memory cell array to provide row selection; wherein both the word-select unit and the section-select unit select a respective column and row of the memory cell array in response to the address information; a profile storage unit connected to said interface comprising a plurality of request profiles that each represent a profile of an access request, wherein each request profile includes: a set of request information elements, wherein at least one of the request information elements indicates whether an access request is a read request or a write request; and access flags, whose state indicates whether a corresponding access request is allowed to access the memory or not allowed to access the memory, the access flags comprising write protect flags and read protect flags; an access control unit connected to said profile storage unit and said memory and configured to allow or reject an access request; wherein said profile storage unit selects an access flag that corresponds to a request profile in response to an access request that fits the request profile; and wherein the access control unit allows or rejects an access request in response to the access flag that is selected by the profile storage unit and wherein a write request that violates a write access flag is ignored and a read request that violates a read access flag results in a fixed answer and wherein a violation triggers an interrupt pin on the interface.
 2. The memory device of claim 1 wherein the profile storage unit comprises a set of access flags, one access flag for each row address, such that each access flag governs the access to one row of the memory cell array.
 3. The memory device of claim 2 wherein the access flags are fast read-out state registers.
 4. The memory device of claim 1 wherein the access control unit operates in the data path to admit or reject a flow of data to or from the memory cell array depending on the state of the corresponding access flag it receives from the profile storage unit.
 5. The memory device of claim 1 further comprising a memory mapped interface and an I/O mapped interface connected to provide access to the memory cell array.
 6. The memory device of claim 5 wherein pins of the memory device are shared by the memory mapped and I/O mapped interfaces. 